1. Field of the Invention
The present invention relates to an oscillation circuit, and more particularly, to a technology accommodating an abnormal control current of an oscillation circuit in which an oscillation frequency is controlled by current.
2. Description of the Related Art
FIG. 4 is a circuit diagram of a related-art oscillation circuit 400.
The related-art oscillation circuit 400 includes a power supply terminal 101, a ground terminal 102, a V/I conversion circuit 103, PMOS transistors 115 and 118, and a current controlled oscillator 104.
The V/I conversion circuit 103 includes a first reference voltage source 111, an error amplifier 112, an NMOS transistor 114, and a resistor 113.
FIG. 5 is a circuit diagram of the current controlled oscillator 104.
The current controlled oscillator 104 includes a capacitor 141, a second reference voltage source 143, a comparator 142, and an NMOS transistor 144.
Connection in the related-art oscillation circuit 400 is described with reference to FIG. 4 and FIG. 5. A non-inverting input terminal of the error amplifier 112 is connected to one end of the first reference voltage source 111. Another end of the first reference voltage source 111 is connected to the ground terminal 102. A gate of the NMOS transistor 114 is connected to an output of the error amplifier 112, and a source thereof is connected to an inverting input terminal of the error amplifier 112 and one end of the resistor 113. Another end of the resistor 113 is connected to the ground terminal 102. A source of the PMOS transistor 115 is connected to the power supply terminal 101, and a gate and a drain thereof are connected to a drain of the NMOS transistor 114. A source of the PMOS transistor 118 is connected to the power supply terminal 101, a gate of the PMOS transistor 118 is connected to the gate of the PMOS transistor 115, and a drain of the PMOS transistor 118 is connected to one end of the capacitor 141, a drain of the NMOS transistor 144, and a non-inverting input terminal of the comparator 142 that are all located in the current controlled oscillator 104. An inverting input terminal of the comparator 142 is connected to one end of the second reference voltage source 143. Another end of the second reference voltage source 143 is connected to the ground terminal 102. A gate of the NMOS transistor 144 is connected to an output of the comparator 142, and a source thereof is connected to the ground terminal 102. Another end of the capacitor 141 is connected to the ground terminal 102.
Operation of the related-art oscillation circuit 400 is now described.
The V/I conversion circuit 103 operates so that a voltage VREF of the first reference voltage source 111 and a source voltage of the NMOS transistor 114 are equal to each other with a negative feedback loop including the error amplifier 112. As a result, a voltage that is equal to the voltage VREF is applied to the resistor 113, and a drain current I1 of the NMOS transistor 114 is a constant current. The PMOS transistors 115 and 118 form a current mirror circuit, and a current I2 directly proportional to the current I1 is supplied to the current controlled oscillator 104.
FIG. 6 is a waveform diagram for showing operation of the current controlled oscillator 104. In the current controlled oscillator 104, the current I2 is a current for charging the capacitor 141, and a slope-like voltage VRAMP is generated at the one end of the capacitor 141. When the voltage VRAMP reaches a voltage VPK of the second reference voltage source 143, an output CMPOUT of the comparator 142 becomes high, the NMOS transistor 144 is turned on, and the capacitor 141 is discharged. The comparator 142 has a detection delay, and thus, the output CMPOUT becomes low with a certain delay time, the NMOS transistor 144 is turned off, and again, the capacitor 141 is charged. Through repetition of the operation described above, the voltage VRAMP has a sawtooth waveform having predetermined amplitude and a predetermined frequency, and the oscillation operation continues.
In Japanese Patent Application Laid-open No. 2001-44808, there is disclosed that, in such a related-art oscillation circuit, the error amplifier 112 is configured such that an upper limit value and a lower limit value of the oscillation frequency can be controlled to be desired values.
However, in the oscillation circuit disclosed in Japanese Patent Application Laid-open No. 2001-44808, through change of the voltage VREF of the reference voltage source 111, a current flowing through the NMOS transistor 114 is changed to control the upper limit value and the lower limit value of the oscillation frequency, and thus, when some troubles are caused in the V/I conversion circuit 103 itself, the current flowing through the NMOS transistor 114 cannot be controlled, and a frequency outside a desired range may be output.
For example, when the resistor 113 is short-circuited and fails, excessive current flows through the NMOS transistor 114 and the frequency exceeds the desired range. Further, on the other hand, when the resistor 113 is open-circuited and fails, the current flowing through the NMOS transistor 114 becomes 0 A and the oscillation operation is stopped.